Implementation of Circuit Using M-GDI Technology ab 45.9 EURO

MGDI technique, in which a low number of transistors are used to reduce the power consumption and area on chip of digital circuits. In this paper the full adder is introduced using MGDI technique. 2 bit comparator, full subtractor were introduced using GDI technique. Then these digital circuits were compared with traditional CMOS transistors in terms of power dissipation, number of transistors, area, speed and delay.

This book presents design of a low power high speed 1-bit ALU in 45nm CMOS technology. Low power high speed circuit design has emerged as a challenging and an emerging field among circuit designers and researchers. A 1-bit ALU is designed in 45nm CMOS technology by using CMOS, nMOS PTL and GDI circuit techniques and its performance characteristics such as power dissipation, delay, power-delay product and number of transistors are compared. GDI technique provides better performance characteristics for designing a low power high speed VLSI circuit. This circuit technique reduces power dissipation, delay, and it also maintains low complexity in the integrated circuit design. This technique is suitable for designing a low power high speed VLSI circuit by using very less number of transistors as compared to other circuit design techniques. This technique has emerged as an effective circuit technique for designing a low power high speed VLSI circuit. The contributions made in this book would help circuit designers and researchers in designing low power high speed integrated circuits.

This book introduces a Gate Diffusion Input (GDI) methodology as an alternative approach in digital circuits. In this technique, a wide range of complex logic functions can be realized by using a lower number of CMOS transistors. The advantages of using GDI technique are multi-folded. The first is to implement digital gates (i.e. inverters, NAND, NOR, XOR, XNOR, buffers, etc.) with very low propagation delay and high logic level swing. As a second advantage, the GDI-based circuits consume lower power consumption and chip area compared with the CMOS equivalent. This provides a new implementation of digital circuits which are suitable for longer-lasting portable devices, like smartphones, tablets, IoT, etc.. A third advantage is the simplicity of circuit design by using very small cell library. In this book, after a brief review of GDI specifications, we will discuss different architectures of GDI-based digital circuits that have been recently proposed.

As technology scales into the nanometer regime leakage current, active power, delay and area are the important metric for the analysis and design of complex arithmetic logic circuits. In this paper, low leakage 1bit full adder cell are proposed for mobile applications and a novel technique has been introduced with improved staggered phase damping technique and also Gated Diffusion Input (GDI) technique for further reduction in the Active power. Leakage power is being estimated when the circuits are connected with a sleep transistor, Further compared to the Base case and Design1 and Design2 and GDI Technique when a circuit is connected to sleep transistor. We introduced a new transistor resizing approach for 1bit full adder cells to determine the optimal sleep transistor size which reduce the leakage power and Area. The simulation results depicts that the proposed design also leads to efficient 1bit full adder cells in terms of standby leakage power, active power. We have performed simulations using Microwind 90nm standard CMOS technology at room temperature with supply voltage of 1V.